Dr. Kaushik Chandra Deva Sarma
Assistant Professor • Department of Instrumentation Engineering
Scholarly Indexes & Profiles
Assistant Professor
Instrumentation Engineering
Faculty In charge (Gym), Faculty In charge (Library Research Work))
Dr. Kaushik Chandra Deva Sarma
Institutional Email
kcd.sarma@cit.ac.in
Intercom / Phone
+91 9706490533
Academic Campus
CIT Kokrajhar, BTR, Assam
Specialization & Research Thrusts
Research Interests: Semiconductor Devices, Power Electronics, Optoelectronics, Sensors
Institute of Technology Kokrajhar
Extra Curricular Interests: Bodybuilding, Power lifting
Academic Background
Educational Qualifications & Pedagogy
PhD(Tezpur University),M.Tech(Tezpur University)
Scholarly Footprint
Peer-Reviewed Publications (26)
| # | Publication Title | Journal / Venue | Authors | Publisher | ISSN / ISBN | Year |
|---|---|---|---|---|---|---|
| 1 | An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor | Journal of Computational Electronics | KCD Sarma and S Sharma | Springer | — | 2015 |
| 2 | A Potential Model for Parallel Gated Junctionless Field Effect Transistor | Silicon | AK Raibaruah and KCD Sarma | Springer Nature | — | 2021 |
| 3 | A Method for Reduction of Off State Leakage Current in Symmetric DG JLT | Engineering Research Express Vol Vol. 1, No. 1 | K C D Sarma and S. Sharma | IOP Publishing | — | 2019 |
| 4 | A Physics Based Approach for Threshold Voltage Modelling of Symmetric Double Gate Junctionless Transistor With Multi Material Gate | Journal of Nanoelectronics and Optoelectronics Vol Vol. 13, No.4 | K C D Sarma | American Scientific Publishers | — | 2018 |
| 5 | An Analytical Approach for Drain Current Modelling of A Symmetric Double Gate Junctionless Transistor | Journal of Nanoelectronics and Optoelectronics Vol Vol. 13, No.9 | KCD Sarma and S Sharma | American Scientific Publishers | — | 2018 |
| 6 | Carrier Mobility Enhancement of Symmetric Double Gate Junctionless Transistor | Journal of Nanoelectronics and Optoelectronics Vol Vol. 12, No.4 | KCD Sarma and S Sharma | American Scientific Publishers | — | 2017 |
| 7 | Scale Length Determination of Gate All Around (Regular Hexagonal Cross Section) Junctionless Transistor | International Journal of Applied Engineering Research Vol Vol. 10, No.2 | KCD Sarma and S Sharma | Research India Publications | — | 2015 |
| 8 | Microcontroller Based Optical power meter for Lab Applications | Journal of Instrument Society of India Vol Vol. 40, No.6 | K C D Sarma, A Mallik, A Bhatnagar | Instrument Society of India | — | 2010 |
| 9 | Threshold Voltage and Flatband Voltage of Normally on Junction Less Field Effect Transistor | Journal of Nanoelectronics and Optoelectronics Vol 17 | A. Talukdar, K.C.D. Sarma, | American Scientific Publishers | — | 2022 |
| 10 | Modelling of CMOS Inverter Using Normally on JLFET | Journal of Nanoelectronics and Optoelectronics Vol 17 | A. Talukdar, K.C.D. Sarma, | American Scientific Publishers | — | 2022 |
| 11 | Channel potential modeling of Surrounded channel Junctionless Field effect transistor | Journal of Nanoelectronics and Optoelectronics Vol 17 (2) | N. Das, K.C.D. Sarma, | American Scientific Publishers | — | 2022 |
| 12 | Carrier Mobility Analysis of Parallel Gated Junctionless Field Effect Transistor | Journal of Nanoelectronics and Optoelectronics Vol 17(1) | AK Raibaruah, K.C.D. Sarma, | American Scientific Publishers | — | 2022 |
| 13 | Digital Circuit Performance Evaluation of Parallel Gated Junctionless Field Effect Transistor | Journal of Nanoelectronics and Optoelectronics Vol 17 | AK Raibaruah, K.C.D. Sarma, | American Scientific Publishers | — | 2022 |
| 14 | Study of performance evaluation of various characteristics of a single phase full bridge inverter circuit using surrounded channel junctionless field effect transistor | Discover Electronics Vol 1 | N. Das, K.C.D. Sarma, | Springer Nature | — | 2024 |
| 15 | Dependence of Electrical Characteristics of Junctionless FET on Body Material | Procedia Computer Science Vol 171 | A. Talukdar, K.C.D. Sarma, AK Raibaruah | Elsevier | — | 2020 |
| 16 | Resistance based drain current model of Surrounded channel junction less field effect transistor | Journal of Nano and Electronic Physics Vol 16 | N. Das, K.C.D. Sarma, | Sumi State University | — | 2024 |
| 17 | High power analysis of surrounded channel junction less field effect transistor | Journal of Nano and Electronic Physics Vol 16(5) | N. Das, K.C.D. Sarma | Sumi State University | — | 2024 |
| 18 | An Analytical Model for the Depletion Region Width and Threshold voltage of Parallel Gated Junctionless Field Effect Transistor | Journal of Nano and Electronic Physics Vol 14 | AK Raibaruah, K.C.D. Sarma, | Sumi State University | — | 2022 |
| 19 | A Simulation Study of DC-DC Boost Converter Using Double Gate Junctionless Field Effect Transistor with Triangle Shaped Spacer | INTERNATIONAL JOURNAL OF NANOELECTRONICS AND MATERIALS Vol 18(2) | A. Baro, KCD Sarma | UNIVERSITI MALAYSIA PERLIS | — | 2025 |
| 20 | A high efficiency boost converter topology with least component count | Indonesian Journal of Electrical Engineering and Computer Science Vol 99 | R. Swargiary, K.C.D. Sarma | Institute of Advanced Engineering and Science (IAES) | — | 2025 |
| 21 | An Enhanced Buck-Boost Converter Performance using snubber circuit and advanced semiconductor devices | INTERNATIONAL JOURNAL OF NANOELECTRONICS AND MATERIALS Vol 18(1) | R. Swargiary, K.C.D. Sarma | UNIVERSITI MALAYSIA PERLIS | — | 2025 |
| 22 | Potential Modelling of Double Gate Junctionless Field Effect Transistor with Triangle Shaped Spacer | Journal of Nanoelectronics and Optoelectronics Vol 20(2) | A. Baro, KCD Sarma | American Scientific Publishers | — | 2025 |
| 23 | A Simulation Study on the Performance of Double Gate Junctionless Field Effect Transistor for Doping Concentration Variation ,” Journal of Nano-and Electronic Physics | Journal of Nanoelectronics and Optoelectronics Vol 16 (5) | P. Saikia, A.K. Raibaruah, and K.C.D. Sarma | Sumi State University | — | 2024 |
| 24 | A Simulation Study of DC-DC Boost Converter Using Double Gate Junctionless Field Effect Transistor with Triangle Shaped Spacer | Indonesian Journal of Electrical Engineering and Computer Science | A. Baro, KCD Sarma | Institute of Advanced Engineering and Science (IAES) | — | 2024 |
| 25 | An Analytical Method for Determination of Threshold Voltage of Surrounded Channel Junctionless field effect transistor | Journal of Nano and Electronic Physics | N. Das, R. Swargiary, K.C.D. Sarma | Sumi State University | — | 2025 |
| 26 | An Analytical method for Determination of Threshold voltage of Surrounded channel Junctionless Field effect Transistor | Journal of Nano and Electronic Physics | N. Das, K.C.D. Sarma | Sumi State University | — | 2025 |
Academic Symposia
National & International Conferences Attended (4)
| # | Presentation / Paper Title | Venue / Place | Publisher / Organizer | Period |
|---|---|---|---|---|
| 1 | International Conference on Computational Performance Evaluation (ComPE) | North Eastern Hill University, Shillong, India | IEEE | 2020/2020 |
| 2 | International Conference on Computational Performance Evaluation (ComPE) | North Eastern Hill University, Shillong, India | IEEE | July/2020 |
| 3 | International Conference on Computational Performance Evaluation (ComPE) | North Eastern Hill University, Shillong, India | IEEE | July/2020 |
| 4 | International Conference on Computational Performance Evaluation (ComPE) | North Eastern Hill University, Shillong, India | IEEE | July/2020 |
Dr. Kaushik Chandra Deva Sarma
Ph. D. Produced:
1. Namita Das, "Design and Analysis of Surrounded Channel Junctionless Field Effect Transistor for Power Electronic Circuit Applications" 2025
2. Angshumala Talukdar Mathematical Modeling and Circuit Performance Enhancement of Normally On Junction less field Effect Transistor
3. Apurba Kumar Raibaruah, Performance Enhancement of Junction less Field Effect Transistor with Structural Modification
,Central
Patents filed and published:
Patent published on, “U-Shape Spacer Junctionless field-effect transistor (JLFET),” Indian Official Journal of the Patent Office,
Patent Application 202431087934, 22 Nov. 2024.
Patent published on, “A double gate junctionless field-effect transistor (DGJLFET) with hexagonal cross-section,” Indian Official
Journal of the Patent Office, Patent Application 202531008531, 14 Feb. 2025.
Achievments:
Gold Medal in Tripura Bodybuilding Championship Heavyweight category, NPC India, 2025